1. Field of the Invention
The present invention relates to a MOS (Metal Oxide Semiconductor) field effect transistor whose blocking voltage appearing between a drain electrode and a substrate (between a drain electrode and a source electrode) is higher than 5 volts inclusive.
2. Description of Related Art
For implementing a flash memory or the like device which requires a voltage of about 10 volts or higher for memory cell write/erase operations, there are required MOS field effect transistors (MOSFETs) whose blocking voltage is on the order of 10 volts. In Japanese Patent Application Laid-Open Publication No. 8580/1995 (JP-A-7-8580), a MOS field effect transistor which exhibits a relatively high blocking voltage of about 30 volts and in which a high-density layer formed in contact with a drain electrode is disposed relative to a high-density layer formed in contact with the source electrode with interposition of an insulation film having a thickness greater than a gate insulation film.
Further, as the MOS field effect transistor having the blocking voltage in the range of about 10 to 30 volts, there are known those implemented in a so-called LDD (Lightly Doped Drain) structure in which an end of a high-density layer contacted to the drain electrode is disposed with a distance from an end of the gate insulation film with a view to ensuring a high blocking voltage.
It is further noted that in IEDM 89 (IEEE Electron Device Meeting 1989) p. 617, a MOS field effect transistor of such structure is disclosed in which an field relaxation layer and a punch-through stopper layer (halo-layer) each implanted in a gate overlap structure are disposed asymmetrically on the drain side and the source side, respectively.
However, with the hitherto known structures of the conventional MOS field effect transistors, implementation of the transistor in more minute or miniaturized structure has been considered practically difficult or impossible in respect to the blocking voltage to be ensured. Such being the circumstances, even though the memory cells trend to be further miniaturized, the spatial proportion which the MOS field effect transistors of high blocking voltage occupy in the flash memory as a whole is large, rendering it difficult to realize miniaturization of the memory chip.
At this juncture, it should be noted that in the case of the MOS transistor structure disclosed in IEDM 89 (IEEE Electron Device Meeting 1989) p. 617 mentioned above, the voltage to be handled is as low as on the order of 3.5 volts, and no consideration is paid to the handling of high blocking voltage on the order of 5 volts.